1. Field of the Invention
The present invention relates to semiconductor fabrication technology, and more particularly to a semiconductor device that is fabricated using SALICIDE (Self Aligned Silicide) process.
2. Description of the Background Art
In recent years, semiconductor devices have been miniaturized and improved in performance, and at the same time, system LSIs have been proposed. In such a system LSI, for improving its performance, it is required to decrease resistance of a gate pattern and active regions of source and drain. As shown in xe2x80x9cSemiconductor Worldxe2x80x9d, May 1998, page 66, salicide process has been used to decrease that resistance. Especially for SOI (Silicon-On-Insulator) type of devices, the salicide process is important. SOI technology has become increasingly important in the field of integrated circuits. In SOI fabrication, a layer of semiconductor material overlies an insulating layer, typically, a single crystal layer of silicon overlies a layer of silicon dioxide, which itself overlies a silicon substrate.
According to a conventional method, a BOX (Buried Oxide) layer is formed on a silicon substrate. Next, a field oxide layer and a SOI (Silicon on Insulator) layer are formed on the BOX layer. The SOI layer is usually designed to have a thickness of 50 nm to 100 nm. A gate oxide layer is formed on the SOI layer, and a poly-silicon gate layer is formed on the gate oxide layer. A gate side wall layer is formed on the SOI layer to surround the poly-silicon gate layer and gate oxide layer.
Before a first RTA (Rapid Thermal Annealing) process, thus fabricated structure is covered with Co (cobalt) layer and TiN (Titanium Nitride) layer. In the first RTA process, silicide reaction occurs at the junction area between the SOI layer and the Co layer, and between the poly-silicon gate layer and the Co layer, so that the SOI layer and gate layer are silicided. The silicide regions are of CoSi, which still have a high resistance. After the first RTA process, the remaining metal (Co and TiN) are selectively removed by a wet process using such as ammonia water or hydrogen peroxide solution.
Next, the second RTA process is carried out so that silicon in the SOI layer and poly-silicon gate layer again react with the silicide regions. As a result, the silicide regions become to be of CoSi2, which have lower resistance.
According to the above described conventional method, low resistance wiring can be realized by the salicide process. For further improving performance of SOI devices, it is required to make the SOI layer much thinner, for example less than 70 nm. If the SOI layer is formed to have irregular thickness, thinner parts of the SOI layer may be salicided entirely and voids may be made in the SOI layer. If voids are made in the SOI layer, the BOX layer may be etched when contact holes are formed on the active areas. If the silicon substrate is etched as well in worst case, the silicon substrate is electrically connected to the upper electrode. As a result, undesirable electrical leakage is made.
Accordingly, an object of the present invention is to improve quality of a semiconductor device even if a SOI layer is designed to be very thin.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, in a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silicon layer is formed over the entire surface; and a second RTA process is performed to form a second-reacted silicide region.
The main feature of the present invention is to form the supplemental silicon layer over the entire surface prior to the second RTA process. According to the present invention, silicon for silicide process is also provided from the supplemental silicon layer in the second RTA process. As a result, low resistance wiring can be well realized by the salicide process even if an SOI layer is formed to be thinner. Consequently, the fabricated semiconductor device is prevented from having a problem of electrical leakage.
The silicide material may include cobalt (Co) or titanium (Ti). The supplemental silicon layer may be of poly-silicon formed by CVD (Chemical Vapor Deposition) technique. The supplemental silicon layer may be of a-Si (amorphous silicon) formed by sputtering technique.
An impurity may be doped into the supplemental silicon layer before the second RTA process, wherein the impurity is of the same type as active regions. When such an impurity is doped into the supplemental silicon layer, the remaining (non-reacted) silicon can be removed at a high etching rate and high selectivity after the second RTA process. Further, the type of impurity is the same as that of the impurity doped into the corresponding active region, so that the silicide reaction progresses smoothly.
The impurity may be doped into one of N-channel region and P-channel region. When impurity is doped one of N and P channel regions, the silicide reaction can be well controlled between the N-channel region and P-channel region.
According to a second aspect of the present invention, a semiconductor device is fabricated by the above described method of the first aspect of the present invention.